Central processing unit

Results: 2609



#Item
501Virtual memory / Central processing unit / CPU cache / Mmap / Page table / Translation lookaside buffer / C dynamic memory allocation / Radix tree / Page / Memory management / Computing / Computer memory

RadixVM: Scalable address spaces for multithreaded applications Austin T. Clements, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL A BSTRACT

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Source URL: pdos.csail.mit.edu

Language: English - Date: 2015-04-29 10:31:16
502Parallel computing / Classes of computers / Central processing unit / Microprocessors / SIMD / Microarchitecture / Superscalar / Benchmark / X86 / Computer architecture / Computing / Computer hardware

Scalable Vector Media-processors for Embedded Systems Christoforos Kozyrakis Report No. UCB/CSD

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Source URL: iram.cs.berkeley.edu

Language: English - Date: 2002-11-11 15:02:46
503Cache / Central processing unit / Computer memory / Sandy Bridge / L3 / Computing / Computer hardware / Computer architecture / CPU cache

CHAPTER EIGHT Writing Centers and WAC JOAN A.

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Source URL: wac.colostate.edu

Language: English - Date: 2011-03-11 16:52:44
504Cache / Central processing unit / Computer memory / Sandy Bridge / L3 / Computing / Computer hardware / Computer architecture / CPU cache

Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 1 Part 7: L3$/URB (Ivy Bridge) For the 2012 Intel® Core™ Processor Family

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Source URL: files.renderingpipeline.com

Language: English - Date: 2013-09-24 10:27:25
505Computer hardware / Compiler optimizations / CPU cache / Central processing unit / Data / Memory hierarchy / Cache-oblivious algorithm / Loop tiling / Cache / Computer memory / Computing

The Cache Performance of Blocked Monica S. Lam,

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Source URL: suif.stanford.edu

Language: English - Date: 2003-10-16 22:29:20
506Instruction set architectures / Control register / X86 architecture / Pointer / Processor register / ARM architecture / Computer architecture / Computing / Central processing unit

Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 1 Part 5: Graphics Core™ – Video Codec Engine Command Streamer (Ivy Bridge) For the 2012 Intel® Core™ Processor Family

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Source URL: files.renderingpipeline.com

Language: English - Date: 2013-09-24 10:26:51
507Instruction set architectures / Central processing unit / Assembly languages / Instruction set / Addressing mode / X86 / Opcode / Operand / MOV / Computer architecture / Computing / Machine code

Paradyn Parallel Performance Tools InstructionAPI Programmer’s Guide 8.2 Release Aug 2014

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Source URL: www.paradyn.org

Language: English - Date: 2014-08-19 15:19:29
508Computer memory / Central processing unit / Microprocessors / Parallel computing / Digital electronics / Random-access memory / Supercomputer / Exascale computing / CPU design / Computing / Computer hardware / Electronic engineering

Exascale Computing Technology Challenges John Shalf1, Sudip Dosanjh2, and John Morrison3 1 NERSC Division, Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, California 94611

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Source URL: www.nersc.gov

Language: English - Date: 2011-09-09 16:33:03
509Central processing unit / Accumulator / Overflow flag / Flag / Apollo Abort Guidance System / NAR 1 / Computing / Computer architecture / Computer hardware

NUMBER SCALING FOR THE LGP-27 SCALING The LGP-21 considers all numbers to be within the range -lAdd to Reading List

Source URL: www.ed-thelen.org

Language: English - Date: 2008-07-23 04:19:34
510Central processing unit / Models of computation / Computer architecture / Classes of computers / Programming language implementation / Dataflow / Reduced instruction set computing / Pointer / Instruction set / Computing / Computer engineering / Software engineering

Automated Reverse Engineering Halvar Flake – Black Hat Asia 2003 Outline for the talk (I) Theoretical (Dry!) parts first, more “practical” in the second half •

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Source URL: www.blackhat.com

Language: English - Date: 2014-12-16 19:06:21
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